The Palladium Z1 platform executes up to 2304 parallel jobs and scales up to 9.2 billion gates, addressing the growing market requirement for emulation technology.
17 Nov 2015 | 5415 Views | By Autocar Professional Bureau
Cadence Design Systems today unveiled the Cadence Palladium Z1 enterprise emulation platform, the industry’s first datacenter-class emulation system, delivering up to 5X greater emulation throughput than the previous generation, with an average 2.5X greater workload efficiency than the closest competitor. With enterprise-level reliability and scalability, the Palladium Z1 platform executes ...
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Cadence Design Systems today unveiled the Cadence Palladium Z1 enterprise emulation platform, the industry’s first datacenter-class emulation system, delivering up to 5X greater emulation throughput than the previous generation, with an average 2.5X greater workload efficiency than the closest competitor. With enterprise-level reliability and scalability, the Palladium Z1 platform executes up to 2304 parallel jobs and scales up to 9.2 billion gates, addressing the growing market requirement for emulation technology that can be efficiently utilized across global design teams to verify increasingly complex systems-on-chip (SoCs).
“The design and verification of our very complex devices requires us to employ sophisticated tools such as hardware emulation for fast and reliable system development,” said Narenda Konda, director of engineering at NVIDIA. “Due to the Palladium Z1 platform's capacity to handle our billion gate-class designs and its highly sophisticated debug and advanced multiuser capabilities, all in a small form factor, we will be able to design and deliver our next generation GPU and Tegra designs with high quality and on schedule.”
A true datacenter resource enabling maximum utilization, Palladium Z1 enterprise emulation platform features a rack-based blade architecture to provide enterprise-class reliability, a 92 percent smaller footprint and 8X better gate density than the Palladium XP II platform. Optimizing the utilization of the emulation resource, Palladium Z1 platform offers a unique virtual target relocation capability, and payload allocation into available resources at run time, avoiding re-compiles. With its unique massively parallel processor-based architecture, Palladium Z1 platform offers 4X better user granularity than its nearest competitor.
“For our advanced SoC designs, we are facing thousands of verification payloads of varying sizes from dozens of different projects,” said Daniel Diao, deputy general manager of the Turing Processor Business Unit at Huawei. “The Palladium Z1 platform uniquely met our requirements due to its reliability as a datacenter compute resource, offering advanced multi-user capabilities and scalability from small four million gate verification payloads to multi-billion gate designs, allowing us to ensure system functionality in short project schedules.”
Additional key features and benefits of the Palladium Z1 platform include:
- Less than one-third the power consumption per emulation cycle of the Palladium XP II platform. This is enabled by an up to 44 percent reduction in power density, an average of 2.5X better system utilization and number of parallel users, 5X better job queue turnaround time, up to 140 million gate per hour compile times on a single workstation, and superior debug depth and upload speeds
- Full virtualization of the external interfaces using a unique virtual target relocation capability. This enables remote access of fully accurate real world devices as well as virtualized peripherals like Virtual JTAG. Pre-integrated Emulation Development Kits are available for USB and PCI-Express interfaces, providing modeling accuracy, high performance and remote access. Combined with virtualization of the databases using Virtual Verification Machine capabilities, it allows for efficient offline access of emulation runs by multiple users
- The industry’s highest versatility with over a dozen use models, including In-Circuit Emulation running software loads, Simulation Acceleration that allows hot swapping between simulation and emulation, Dynamic Power Analysis using Cadence Joules™ RTL power estimation, IEEE 1801 and Si2 CPF based Power Verification, Gate-level acceleration and emulation, and OS bring-up for ARM-based SoCs running at 50X the performance of pure standard emulation
- Seamless integration within the Cadence System Development Suite. This includes Incisive verification platform for simulation acceleration, Incisive vManager™ for verification planning and unified metrics tracking, Indago Debug Analyzer and Embedded Software Apps for advanced hardware/software debug, Accelerated and Assertion-Based Verification IP, Protium FPGA-based prototyping platform with common compiler, and Perspec™ System Verifier for multi-engine system use-case testing
“We continue to see customer demand for doubling of available emulation capacity every two years, driven by short project schedules amid growing verification complexity and requirements on quality, hardware-software integration, and power consumption” said Daryn Lau, vice-president and general manager, Hardware and System Verification, Cadence. “With Palladium Z1 platform as one of the pillars of the System Development Suite, design teams can finally utilise emulation as a compute resource in the datacenter akin to blade server-based compute farms for simulation, and improve schedules while enabling more verification automation to address the growing impact of verification on end product delivery.”